1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a write/erase control sequence thereof.
2. Description of the Background Art
A flash memory is known as a nonvolatile semiconductor memory device. The flash memory has a memory array in which memory cells are two-dimensionally arranged, and a controller (CPU) for controlling write and erase operations. The flash memory stores a sequence (program) serving as software for controlling write and erase operations therein.
In a prior art flash memory, a plurality of flag areas are formed when a rewrite program is written in the flash memory. The flash memory has a controller which performs decisions of the ends of a plurality of steps of the rewrite process or decisions of true and false of the steps to record the results in the flag areas, respectively (Japanese Laid-open Patent Publication No. 2000-105694).
Of a write operation and an erase operation of a flash memory, the erase operation has a complex sequence. Although one erase operation for the sequence requires several seconds in a practical device, execution of the simulation (verification) may require several tens of hours. However, when the simulation time becomes long, the sequence may be interrupted along the way. For example, a defect may be detected in the middle of the sequence, and the execute of the sequence may be interrupted along the way due to the simulation tool. Even though the simulation is completed in the first half of the sequence, the long sequence must be continuously executed from the first to the end again to perform the simulation of the second half. In this case, even though the sequence is executed from the middle of the sequence by jumping over the first half, the state of the sequence part skipped by the jump is not matched with the state of the second half of the sequence, and accurate simulation cannot be performed with good matching as a whole. In this manner, the elongation of the simulation time is one of factors which extend development periods.